1. Field of the Invention
The present invention relates to a transfer circuit for signal lines and utilized, for example, for selectively transferring one of a plurality of local data buses to a common data bus.
2. Description of the Related Art
In a static random access memory (SRAM), a memory cell array is divided into a plurality of blocks, to obtain a low power consumption or a high speed processing. In this case, one of a plurality of local buses connected to the memory cell array block must be selected and the data thereon transferred to a common data bus. This selection and transfer are carried out by a transfer gate circuit.
In a transfer circuit for signal lines using a transfer gate, since all of the transistors are MIS (metal insulator semiconductor) transistors, the resistance in a conductive state is relatively high, the overdrive voltage is low, and the local data bus has a large electrostatic capacity due to the connection of many memory cells. Therefore, a time constant for a charge in the bus is long, and a problem arises in that it takes a long time to transfer data from the local data bus to the common data bus.
The present invention is intended to provide a high speed transfer circuit for signal lines by using a bipolar transistor and MIS transistors.